New version of SYSTEM CASCON increases test throughput

Generation and execution of test vectors results in test time savings

The software package SYSTEM CASCON, which enables Embedded JTAG Solutions, receives an update. The new version 4.6.8 uses a number of new techniques to more efficiently generate and execute test vectors for various applications. These techniques result in time savings and increased test throughput.

The new software version is optimized for the hardware platform SCANFLEX II, unlocking its full potential. Together, the system represents the most modern JTAG / Boundary Scan architecture on the market. It enables truly independent parallel scanning on up to 8 TAPs (Test Access Port) simultaneously with 100MHz clock frequency and full signal delay compensation. Particularly important for performance is the advanced SPACE III technology for data compression. Test procedures can be significantly accelerated with optimized SYSTEM CASCON control. This benefits complex RAM interconnection tests, massive SVF (Serial Vector Format) based tests, VarioTAP Processor Emulation Test procedures and ChipVORX procedures for FPGA Assisted Test.

SYSTEM CASCON offers more than 40 tools for Boundary Scan/IEEE1149.x applications including Processor Emulation Test, FPGA Assisted Test, Embedded Diagnostics, Design Validation, Debugging and various in-system programming strategies. This allows the user to develop and run all embedded JTAG Solutions technologies in order to test and program complex designs with reduced physical access and on a single platform.

Embedded JTAG Solutions System Software

Embedded JTAG Solutions System Software Version 4.6.8

Created by Matthias Müller | | Embedded JTAG Solutions Software

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