ChipVORX is an IP-based technology for implementation, access and control of Chip embedded Instruments via IEEE Std. 1149.x/JTAG. It also supports FPGA embedded instruments in the form of softcores. The ChipVORX library currently contains more than 300 different test and measurement instruments for all leading FPGA platforms. The usage of ChipVORX requires neither expert background knowledge nor specific FPGA tools or continuous IP adjustments.
The FPGA-integrated ChipVORX models are functional software IPs with a modular architecture. This allows you to configure FPGAs individually to use them for functional testing. The capabilities already provided by FPGAs or CPLDs are used to increase test coverage and speed.
- high-speed in-system flash programming
- High-speed access test of DDR-SDRAM (at-speed access)
- universal frequency and clock measurements
- Bit Error Rate Test (BERT)
- Control of IEEE-1687 instruments (IJTAG) as well as pure IEEE-1149.1 instruments
- interactive tests with boundary-scan operations
ChipVORX SI is an advanced platform using powerful FPGA IPs for test & in-system programming. You can customize universal ChipVORX designs to your specifications and configure them for your needs to enable real-time testing.
The compilation of the FPGA design is completely moved to a cloud and acts in the background. This results in maximum flexibility and easy handling, without any special knowledge of FPGA designs. In addition, you avoid additional programming costs.
ChipVORX SI will support completely new application possibilities in the future.
- Gigabit-Transceiver Bit Error-Rate Test (BERT)
- Frequenzmessung (für differentielle Clock-Signale)
- Ethernet PHY Interface Tests (GMII, RGMII, SGMII, HSGMII, QSGMII, XGMII…)
- Ethernet Frame-Error Rate Test (FERT)
- Unterstützung spezieller I/O Standards
- At-Speed RAM Verbindungstest (DDR3/DDR4 und neuer)
- Nominal-Speed Anforderungen oder angepasste funktionale Testfeatures (LCD Test, Busse (UART…), Protokolle (HDMI…))
Zusätzlich können mit ChipVORX SI mehrere dieser Instrumente (CV und CV SI) in einem einzigen FPGA Design zusammengeführt werden, um mehrfaches Konfigurieren des FPGAs im Testablauf zu vermeiden.