The Expert Level with IP plus

Nominal to stress level test

In the highest expert level, IP Plus, the maximum speeds can be achieved. We are now talking about the nominal or stress level test. At nominal speed, the test is performed at the speed of the pin function. At even higher speeds and/or extended parameters, we speak of the stress-level test. In this case, the specification is even exceeded. The tests in this level show whether your assembly is already working in the limit range or is close to the failure limit.

A typical test application is a Bit Error Rate Test at highspeed interfaces. IP Plus level programming is performed at highest speeds (> MBytes/s), because the programming data are transferred via the communication interface (e.g. Ethernet) as well.

Here in the Expert level, tests and programming are controlled via the JTAG interface or a debug interface, e.g.  via SWD (ARM), DAP (Infineon) and others. The programming data can thereby be transferred past the control interface and via a communication interface 

Common and widely used communication interfaces today are e.g. USB, Ethernet, CAN and others.

The Embedded Board Test at Expert Level

IP-controlled semi-structural test

Applications:

  • FPGA based BERT (Bit Error Rate Test)
    • display of eye diagrams
    • suitable for production through multi point measurement

The Embedded Functional Test at Expert Level

IP controlled functional test

Applications:

  • dynamic access to Non-Boundary-Scan elements
  • functional RAM test, RAM cell test, RAM stress test
  • DDR RAM calibration
  • functional interface tests
  • Ethernet stress test FERT (Frame Error Rate Test)

Embedded Programming at Expert level

IP controlled programming of Flash memories and μControllers

Applications:

  • programming in the Gigabyte range
  • FPGA (Boot-)EEPROM / Flash programming
  • µProcessor OnChip-Flash programming
  • µProcessor Flash rrogramming
  • I2C, SPI, Microwire, NOR, NAND, PCM, eMMC ...
  • use of communication interfaces

Test Speed

The test speed is always related to a pin or a pin group and depends on the intended use in the future application.

Nominal-Speed

Signal changes are similar to the functional speed of the controlling pin(s), e.g. in boot flash programming with an embedded FPGA instrument.

Stress

Signal changes are at exact or higher than function speed and/or deviating parameters of the controlling pin(s).

Programming Speed

The programming speed depends on the amount of data to be transmitted and is dependent on several factors. Without knowledge of the application, precise statements are therefore usually not possible. Information on speed is always subjective and depends on the application.

High to very high programming speed

In the Expert level with IP plus, the highest programming speeds in the range of MBytes/s up to GBytes/s can be realized. Here, the user data can be transmitted via fast communication interfaces, such as Ethernet.

Applications from GÖPEL electronic

The Expert level is applied with the following combinable technologies

  • JTAG-based Test

    The standardised Boundary Scan method according to IEEE 1149.1  can simply control complex components such as FPGAs, processors, controller and CPLDs. Detailed hardware knowledge is not required.

    » Learn more about Boundary Scan

  • FPGA-based Test

    The ChipVORX technology uses the FPGA logic for the test. With the help of universal FPGA models, you can access standardised functionalities without further adjustments. This allows classic boundary scan tests and programming to be significantly accelerated. Untypical tests such as frequency measurement can also berealised.

    » Learn more about ChipVORX

  • µProcessor-based Test

    A processor-specific model brings the IC into debug mode. After that, internal functionalities (registers, memory areas, complex controllers) are addressed to perform analogue measurements, at-speed Flash programming or even at-speed RAM tests. Both the JTAG port and other debug interfaces can be used for this purpose.

    » Learn more about VarioTAP

  • Processor-based test with universal firmware

    JEDOS  performs complex functional tests with a graphic interface. Memory cell tests, ultra-fast flash programming or interface tests (Ethernet, USB, ...) can be created in a very short time without any special hardware knowledge.

    » Learn more about JEDOS

Als The basis for all test and programming procedures is the  hardware architecture SCANFLEX II to control the UUT. 

» Learn more about SCANFLEX II