JTAG/Boundary Scan or the IEEE 1149.1 standard is one of the most successful electronics standards of all time and was invented to test electrical assemblies. JTAG/Boundary Scan has become an integral part of electronics development and production.
A basic test approach is the verification of perfect board connections. Similar to the ICT (In-Circuit-Test), individual conductor paths of the assembly are stimulated at one point and measured at another point. The information from this measurement provides conclusions about possible faults on the printed circuit board. The performance, however, goes far beyond testing connections on boards.
The Embedded JTAG Solutions from GÖPEL electronic are the basis for new, non-intrusive methods and standards for test, debugging, programming and emulation of printed circuit boards.
The Boundary Scan test via the JTAG interface is the classic. JTAG (Joint Test Action Group) provides access to a serial push chain. All Boundary Scan IOs are set and read out via JTAG.
Processors, FPGAs and other advanced chips often have a JTAG-TAP, the Test Access Port. This port is used to access individual boards for configuration, communication and debugging.
The standard itself describes the structure of a JTAG-enabled device, as well as the description language, the "Boundary Scan Description Language (BSDL)". It discloses the unique Boundary Scan resources for each device.
For the internal structure of a Boundary Scan component, the IEEE standard defines four essential components that a Boundary Scan-capable component must have:
Prozessoren, FPGAs und andere hochentwickelte Chips verfügen oftmals über einen JTAG-TAP, den Test Access Port. Über diesen erreicht man einzelne Baugruppen zwecks Konfiguration, Kommunikation und Debugging.
Im Standard selbst ist der Aufbau eines JTAG-fähigen Bausteins dargelegt, wie auch die Beschreibungssprache, die "Boundary Scan Description Language (BSDL)". Sie legt die für jeden Baustein einzigartige Boundary Scan Ressourcen offen.
Zum inneren Aufbau eines Boundary Scan Bausteins definiert der IEEE-Standard hierzu vier wesentliche Bestandteile, über die ein Boundary Scan-fähiges Bauteil verfügen muss:
Test Access Port (TAP)
The "Test Access Port" is the interface between the Boundary Scan logic in the device and the outside world. Three inputs (plus an optional fourth) and one output are described.
The inputs are:
- Test Clock (TCK)
- Test Mode Select (TMS)
- Test Data Input (TDI)
- Test Reset (/TRST) - optional
The output is:
- Test Data Output (TDO)
The two signals TCK and TMS as well as the optional /TRST signal are broadcast signals. The TDI towards the TDO, on the other hand, forms a serial chain, the so-called scan chain or scan path (see figure). At the module level, this is referred to as the test bus.
The brilliant thing about this construction is that never more than four (optionally five) signal lines are needed, regardless of how many components are switched into the scan chain.
In the Boundary Scan device, the "Test Clock", the "Test Mode Select" as well as the "Test Reset" are directly connected to the "TAP Controller", i.e. statically. The signals are solely responsible for its state. This also means that all Boundary Scan devices of a scan chain are always in the same TAP state. This does not automatically mean that all devices must always be in the same operating mode/command.
The "TAP Controller" is responsible for the complete control of the Boundary Scan logic in the device. This means that it is responsible, among other things, for whether a Boundary Scan cell is activated or deactivated and whether it is currently measuring or driving.
The heart of the "TAP Controller" is the "TAP state machine". The states it contains have a different influence on the control of the internal Boundary Scan logic.
The instruction register determines the operating mode of the Boundary Scan device. This in turn influences the control of the Boundary Scan cells as well as the selection of the data register currently connected to the scan chain (register between TDI and TDO). The IEEE 1149.1 standard defines three mandatory commands:
Each command is assigned a corresponding command code (bit code). This can be freely defined by any chip manufacturer (except for the BYPASS command, which must consist entirely of ones). The length of the command register can also be selected at will. An exemplary assignment is shown in the table. The length of the command register was defined as two bits.
Operating Mode / Command Command Code (Binary) BYPASS 11 SAMPLE / PRELOAD 01 EXTEST 00
Data Register (Boundary Scan Register)
A Boundary Scan capable device can contain several data registers. These are used to store information in the block or to read it out.
The standard IEEE 1149.1 describes at least two mandatory data registers:
Also in this case additional registers are possible, like the "device identification" or colloquially also the "idcode" register.
The "bypass" register represents the possibility to detach the device from a network of Boundary Scan devices, i.e. to bypass it. It has a minimum length of only one bit. The value of the bit is unchangeable and defined with 0.
The data register that is much more interesting for later testing is the boundary-scan register, which represents the sequence of the individual boundary-scan cells. Since each chip has a different number of Boundary Scan cells, the length of this register is variable.
Boundary Scan Cell
The Boundary Scan cell is the main component of the Boundary Scan test procedure. All constructs described so far serve only for the correct control of the individual Boundary Scan cells.
The Boundary Scan cell is the brilliant possibility to control the component pin of a device detached from its normal function, i.e. to drive or measure a certain level. For this purpose, the Boundary Scan cell is located between the core logic of the device and its periphery (output driver, input driver). Due to the functional similarity to the physical scanning needles of the in-circuit test procedure, which realize the access to the individual test points there, Boundary Scan cells are also called "electronic nails".
The internal structure of a single Boundary Scan cell can be very different. For example, the IEEE 1149.1 standard in its 2001 version describes ten different cell types (BC_1 to BC_10). Own structures are also possible as well. The design is often very similar.
It is important for the developer to verify and validate the circuits quickly and easily during the design phase. In the production area, however, fast test procedures are used that provide very accurate and detailed error analysis.
A simple and compact test system, such as a notebook PC with a PCMCIA or a USB controller, is advantageous for service/field use. Boundary Scan ensures all these requirements with its consistent use in all phases of product development. GÖPEL electronic provides various Embedded JTAG Solutions Controller for various platforms and applications, such as PCI, PXI, VXI, PCMCIA, USB, Fast Ethernet and additional power and I/O modules.
With the Embedded JTAG Solutions from GÖPEL electronic, flash memories and PLD/FPGAs are programmed in every "life stage" of a product: Embedded Programming. For example, firmware and updates can be transferred at any time. This does not only apply directly to production. Even on a completely assembled device, programming can be carried out at any time with a high TCK frequency (depending on the maximum clock frequency specified by the component manufacturer).