Using the JTAG interface for testing and programming embedded systems - how does that work?
JTAG (Joint Test Action Group) Boundary Scan is a standardized electrical testing method used to test, program and debug assembled printed circuit boards (PCBs).
A JTAG tester uses Boundary Scan software and hardware to detect connection errors, short circuits and soldering errors — even without physical access to all pins. The JTAG interface enables structural and connection tests, as well as extended functional tests, which check the functions of the board and components. This enables pin-accurate failure localization and the elimination of errors in the development and production processes. JTAG Boundary Scan also enables fast programming in the production process.
The problem of testing is as old as the transistor itself. Modern electronics have increasing component complexity with decreasing access possibilities. Test methods such as In-Circuit-Test (ICT) and Flying Probe Test (FPT) are frequently used, but when used in ball grid arrays (BGA), chip scale packages (CSP) and the smallest designs such as 01005, they reach their limits. The crux of the matter is that modern assemblies not only lack the space to contact all signals with needles. Due to negative influences on signal quality, it is becoming increasingly difficult to test with conventional methods. This already posed extreme challenges for developers during the design of new assemblies.
Boundary Scan (IEEE 1149.1 Standard)
The so-called pin electronics of a tester was shifted more and more into the circuit due to the continuously decreasing test access. As a result, a design-integrated pin electronics was developed, which is controlled via JTAG test bus (Joint Test Action Group). This is the approach of Boundary Scan, the IEEE 1149.1 Standard.
The uniqueness is the open expandability of the register architecture as well as the versatility of the JTAG interface and its transmission protocol. These features make JTAG/Boundary Scan a technological basis for new, non-intrusive methods and standards for testing, debugging, programming and emulation: the Embedded JTAG Solutions.
The performance levels of the Embedded JTAG Solutions
The lower standard level is defined by the static test. This standard access refers to the known boundary scan test options. At this level, mainly the classical connection tests are performed; programming is done at low speed.
Higher access speeds are achieved in the Boundary Scan Plus level, as well as in programming.
The highest level, IP Plus, hasn't much in common with the classic JTAG/Boundary Scan. Testing and programming speeds are at the highest level, far above the targeted board functions.
What are Embedded JTAG Solutions?
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The elements of the Embedded JTAG Solutions
- Embedded Board Test
The Embedded Board Test serves the verification of functional board connections. Thus the Boundary Scan, Microcontroller and FPGA resources are used to find short circuits, unsoldered pins or pull resistors in the simplest case.
- Embedded Programming
In addition to the verification of flawless connections and functional testing of a DUT, the programming of various data is also a major challenge. Above all, increasing data volumes and growing demands on programming speed pose a major hurdle. With the help of the Embedded JTAG Solutions, the test system can be optimally adapted to your own requirements.
- Embedded Functional Test
Today's test strategies require more than just the simple testing of board connections. In addition to proper contacting, the board and component functions must also be tested. This is where the Embedded Functional Test is applied.
