Boundary Scan | IEEE 1149.1 | JTAG

Efficient together!
Complete solution for testing & programming electronic assemblies
BARCUDA VP230
JTAG stand-alone system BARCUDA
Beyond boundaries.
Boundless test and programming applications.
Boundary Scan plus und IP plus.
Embedded JTAG ► Beyond boundaries
Test them all!
Automatic interconnection test despite non-boundary-scan capable pins.
SYSTEM CASCON 4.7
Emulation Based Interconnection Test
SYSTEM CASCON - JTAG Software

The problem of testing is as old as the transistor itself. Modern electronics have increasing component complexity with decreasing access possibilities. Test methods such as In-Circuit-Test (ICT) and Flying Probe Test (FPT) are frequently used, but when used in ball grid arrays (BGA), chip scale packages (CSP) and the smallest designs such as 01005, they reach their limits. The crux of the matter is that modern assemblies not only lack the space to contact all signals with needles. Due to negative influences on signal quality, it is becoming increasingly difficult to test with conventional methods. This already posed extreme challenges for developers during the design of new assemblies.

► In-Circuit-Test (ICT) ► Flying Probe Test (FPT)

JTAG/Boundary Scan Hardware and Software

The so-called pin electronics of a tester was shifted more and more into the circuit due to the continuously decreasing test access. As a result, a design-integrated pin electronics was developed, which is controlled via JTAG test bus (Joint Test Action Group). This is the approach of Boundary Scan, the IEEE 1149.1 Standard.

The uniqueness is the open expandability of the register architecture as well as the versatility of the JTAG interface and its transmission protocol. These features make JTAG/Boundary Scan a technological basis for new, non-intrusive methods and standards for testing, debugging, programming and emulation: the Embedded JTAG Solutions.

The lower standard level is defined by the static test. This standard access refers to the known boundary scan test options. At this level, mainly the classical connection tests are performed; programming is done at low speed.

Higher access speeds are achieved in the Boundary Scan Plus level, as well as in programming.

The highest level, IP Plus, hasn't much in common with the classic JTAG/Boundary Scan. Testing and programming speeds are at the highest level, far above the targeted board functions.

► Find an overview of all possible applications

By activating external content from www.youtube-nocookie.com, you consent to transmitting data to this third party.
More Info

Activate once

Embedded Board Test
The Embedded Board Test serves the verification of functional board connections. Thus the Boundary Scan, Microcontroller and FPGA resources are used to find short circuits, unsoldered pins or pull resistors in the simplest case.
Embedded Programming
In addition to the verification of flawless connections and functional testing of a DUT, the programming of various data is also a major challenge. Above all, increasing data volumes and growing demands on programming speed pose a major hurdle. With the help of the Embedded JTAG Solutions, the test system can be optimally adapted to your own requirements.
Embedded Functional Test
Today's test strategies require more than just the simple testing of board connections. In addition to proper contacting, the board and component functions must also be tested. This is where the Embedded Functional Test is applied.