Standard Boundary Scan

The Standard level uses Boundary Scan cells according to IEEE 1149.1 for testing.

The test speed is far below the actual board function.

The classic connection test is one of the main tasks of this level. But also the addressing of components, e.g. for reading out a chip ID or a sensor value, can be realised at this access level.

In programming, only low data rates are usually achieved (ranging from bytes/s to kBytes/s).

Boundary Scan Coach / EZScan - a typical Standard Boundary Scan PCB

The test and programming applications are controlled exclusively via the JTAG interface. All control, test and programming data are transmitted via this interface.

Applications

verification of JTAG Infrastructure
detection of shorts between Boundar Scan Nets
detection of shorts between IEEE 1149.6 Nets
detection of open pins
detection of missing inline resistors
detection of missing or wrong pull resistors
testing beyond multipanel PCBs
use of additional virtual boundary scan I/Os (GPIOs, Flying Probes ...)

Structural and parametric test with Boundary Scan

Applications:

static RAM connection test
static access to non-Boundary-Scan elements
level shifter, Driver ICs, analog switches
logic components
memory, RTC, sensors, PHY…
LED
switches
summer
optocoupler
Embedded BIST, IEEE P1687 support
parametric tests with µprocessor GPIOs, ADCs and DACs

Applications:

programming in the kilobytes data range
(C)PLD/FPGA Configuration with SVF, JAM, STAPL, IEEE 1532
EEPROM / Flash Programming
I²C, SPI, Microwire, NOR, NAND, PCM, eMMC ...

Flash programming and configuration of (C)PLDs/ FPGAs via Boundary Scan

The test speed is always related to a pin or a pin group and depends on the intended use in the future application.

Static

The signal change runs far below the functional speed of the controlling pin(s). Usually, these are boundary scan or GPIO-controlled accesses that run slowly due to the serial shifting processes via the JTAG interface (e.g. the flashing of an LED with confirmation by the operator).

The programming speed depends on the amount of data to be transmitted and is dependent on several factors. Without knowledge of the application, precise statements are therefore usually not possible. Information on speed is always subjective and depends on the application.

Low to medium programming speed

With Boundary Scan, only low programming speeds of a few bytes/s to kBytes/s can be achieved.

JTAG-based Test
The standard Boundary Scan method according to IEEE 1149.1 can simply control complex components such as FPGAs, processors, controller and CPLDs. Detailed hardware knowledge is not required.
» Learn more about Boundary Scan
FPGA-based Test
The ChipVORX technology uses the FPGA logic for the test. With the help of universal FPGA models, you can access standard functions without further adjustments. This allows classic boundary scan tests and programming to be significantly accelerated. Atypical tests such as frequency measurement can also be realised.
» Learn more about ChipVORX
µProcessor-based Test
A processor-specific model brings the IC into debug mode. After that, internal functions (registers, memory areas, complex controllers) are addressed to perform analogue measurements, at-speed Flash programming or even at-speed RAM tests. Both the JTAG port and other debug interfaces can be used for this purpose.
» Learn more about VarioTAP

The basis of all testing and programming is the hardware architecture SCANFLEX II to control the UUT .

» Learn more about SCANFLEX II

The cost-efficient controller SCANBOOSTER II is especially recommended for entry-level users. It is best suited for standard applications with lower performance requirements.

» Learn more about the SCANBOOSTER II