Skip to main content

Webinar: Test Optimization in Production

Reduction of Test Time through the Use of Embedded JTAG Solutions

Learn how you can reduce test time and complex interface hardware through the use of Embedded JTAG Solutions. Both developers and test planners are confronted with the same problem to ensure sufficient access for test despite increasing miniaturization along with a simultaneous increase in the functionality of modern electronics. "On each net a test point!" Many of you know this specification. But this is no longer possible on modern electronics. Get to know in this webinar an essential and cost saving method.

What you will learn

  1. How to turn a device such as an FPGA or microprocessor into an embedded test system.
  2. How testing that previously required high numbers of access pins can still be done when physical external access is no longer possible.
  3. What technologies are available for the reduction of test time. 

Who should attend

  • Test Engineers
  • Test Executives
  • Production Engineers
  • Production Executives
  • CEOs
  • Contract Designers
  • Contract Manufacturers
  • Design Engineers
  • Design Executives

Speaker
Daniel Robertson, GOEPEL electronics Ltd

 

Register Now!

Facts Webinar: Test Optimization in Production
06 Sep 2017 10:00 11:00
Organisator
Frank Amm
Frank Amm
+49-3641-6896-741 Fon
+49-3641-6894-945 Fax