BSDL Testwriter™

The BSDL Testwriter™ software is a tool for the automated generation of a test bench for Boundary Scan designs. It processes BSDL files as input and generates vectors for functional verification of all Boundary Scan structures.
Automating the verification process, manual errors are avoided and the test efficiency is substantially improved.
The BSDL Testwriter™ can optionally generate a STIL (IEEE Std 1450) output. This link allows the use of the generated vectors for a production test of the physical IC on automated test equipment (ATE).

The verification of Boundary Scan structures for IEEE 1149.1 compatibility and design specifications is very time and cost consuming without respective tools. Using the BSDL Testwriter IC design engineers can minimize the number of verification iterations by simulating the generated test bench. Furthermore, human errors are avoided and the overall efficiency of the verification process is substantially improved. If the STIL output is used, the BSDL Testwriter™ can also be used in production. The generated test patterns can be linked to a respective IC tester and can be used for the verification of the physical chip. The quality of the generated test bench ensures highest fault coverage. So the test engineer also benefits from the BSDL Testwriter™.
The generated Verilog or VDHL test bench allows the application of the vectors on all industrial standard simulators. To support the workstation environments typically used for ASIC/ ASSP design the BSDL Testwriter™ was developed for SOLARIS 2.6+ and Windows.

Package/ Option

Order No.

Syntax Checks

Semantic Checks

Compliance Checks

AIM Technology

PMA Technology

Output*

BSDL Testwriter for SOLARIS

233-000

v

v

v

v

v

STIL/ VHDL/ Verilog

BSDL Testwriter for Windows

233-001

v

v

v

v

v

STIL/ VHDL/ Verilog

Additional vector output

233-102

STIL/ VHDL/ Verilog