Embedded System Access (ESA) - test-focused
Access printed circuit boards (electronic PCB)
with Embedded System Access technologies.
JTAG/Boundary Scan Test (BST) for electronic PCBs
In 1990, Boundary Scan was adopted as the IEEE 1149.1 standard. This technology utilises so called boundary scan cells, combined into a Boundary Scan register, as primary access points for a target system’s circuit nodes. The Boundary Scan register is accessed and controlled through the Test Access Port (TAP).
All vectors are serially scanned. The test bus is comprised of four mandatory signals and a fifth optional reset signal. Boundary Scan is a structural methodology and provides excellent fault diagnostics, especially for connectivity tests on BGA devices, for example.
However, since Boundary Scan tests are static in nature, dynamic defects usually cannot be detected, let alone be diagnosed. In addition to IEEE Std. 1149.1, various related IEEE 1149.x standards have been created or are in development to expand fault coverage and to get access to printed circuit boards (electronic PCBs).
Processor Emulation Test (PET)
The Processor Emulation Test (PET) utilises the debug interface (implemented in many micro processors for software validation) to transform the processor core temporarily into a native test controller.
In this case, the processor itself becomes the access point for the connected circuitry in the target system. Remote-controlled through the JTAG interface or some other debug interface, the processor core utilises write and read access to the system bus with respective test vectors in order to manipulate and test the connected internal and external resources and components. No operating system or flash firmware is necessary to accomplish this.
The technology can detect both static and dynamic defects; however, diagnostics are limited due to the functional test approach. PET complements Boundary Scan very well and enables or improves especially the test of dynamic components such as DDRSDRAM, gigabit interfaces, and other non-scannable components at chip, board, and system level.
Chip-embedded Instruments (IJTAG)
Chip-embedded Instruments are essentially test and measurement intellectual property (IP) blocks integrated into ICs, often accessible through the JTAG port.
The functionality of Chip-embedded Instruments is completely open and ranges from simple sensors, to complex signal processing and data collection, through to complete analysis instruments and programming engines. The IP is either integrated permanently in the chip (hard macro) or it can be temporarily instantiated and configured (soft macro) in field programmable gate arrays (FPGA).
This specific form is also referred to as „FPGA Assisted Test (FAT)“ or „FPGA Assisted Programming (FAP).“ Chip-embedded Instruments have been utilised for years in chip testing, for instance, in the form of a built-in self-test (BIST) IP.
Another example is the logic scopes integrated into FPGA for design validation. However, access to these instruments has, until recently, not been standardised, a situation that will change with the launch of the new IEEE P1687 (also known as IJTAG). Hence, standardised Chip-embedded Instruments present an alternative, especially in the field of gigabit analysis, to the traditional testing and measurement instruments with their increasing access problems.
* depending on instrument and implementation