Software Reconfigurable Instruments
There is no doubt that the growing number of ESA technologies are making possible a continuous improvement in the control problems prevalent while testing, programming and validating state-of-the-art electronics at chip, board, and system level. In contrast, vendors of proper testing equipment are facing a severe challenge.
GOEPEL electronic detected this problem early on and pursued the approach known as „Software Reconfigurable Instruments“. This aims to dynamically adapt hardware and software tools to the actual target mission by means of appropriate IPs. The system is essentially based on the following technologies:
Boundary Scan Software SYSTEM CASCON™
By integrating the IP-based technologies into SYSTEM CASCON, the original boundary scan tool suite was developed into an open software/hardware-related platform that supports all ESA strategies.
Software IP-based Technology from GOEPEL electronic
VarioTAP® Emulation Technology
VarioTAP is a revolutionary technology for the fusion of Boundary Scan and processor emulation. It uses VarioTAP models to adapt platform modules to the target processor. The models are modularly defined as intelligent software IP and basically offer a multi-level functional structure.
In principle it is possible – in combination with SCANFLEX hardware, which is also adapted dynamically through software to the corresponding debugging interface (JTAG, BDM, SBW, SWD, COP, etc.) – to support all contemporary processors and micro controllers. The same applies to multi-processor and multi-core designs.
Thanks to innovative ChipVORX technology, it was possible to combine Boundary Scan and Chip-embedded Instruments for the first time. ChipVORX models are used to adapt software tools to the target instruments. As a result, the technology is completely open for any type of instrument:
- FPGA-loaded instruments (soft macros)
- IP vendor proprietary instruments (hard macros)
- standardised instruments access (IJTAG macros)
- custom-designed instruments (ASIC hard macro)
IC-centered ChipVORX models are functional software IPs with a modular architecture. This openness serves to simultaneously support several embedded instruments. The same applies if the instruments are embedded in different chips.
FPGA-based instruments are particularly significant, because they enable extremely flexible applications. In this case, too, ChipVORX offers an excellent solution, because it supports ESA technologies such as FPGA-Assisted Test (FAT) and FPGA-Assisted Programming (FAP); at the same time, it is able to handle soft macros and the required loading into the target FPGA. This means that ChipVORX models for FPGA are not only able to access and control instruments, they can also contain such instruments. This type of ChipVORX model focuses on applications such as:
- high-speed flash In-System Programming
- high-speed access test of DDR-SDRAM
- universal frequency and clock measurements
- bit error rate test (BERT)
VarioCore is a revolutionary technology for the reconfiguration of I/O modules. These modules include:
VarioCore IPs, which dynamically adjust the functional scope of a module to the appropriate test task, serve as their basis. In doing so, the VarioCore IPs can be activated in sequence and can be immediately accessed and controlled, i.e. without having to reinitialise the platform. The available functions include:
- counter/frequency measurement IP
- vector generator/recorder IP
- digitiser/bus emulator IP
- customer-specific IP
JEDOS - JTAG Embedded Diagnostics Operating System
Embedded Functional Test, Diagnostics, Calibration and Programming
JEDOS™ is an embedded test & diagnostics operating system of the next generation. It is able to perform functional tests in real time using the native processor. The use of special test software or Flash resident firmware thus is completely unnecessary.
JEDOS™ provides maximum fault coverage and comprehensive diagnoses for digital, analog and mixed-signal components. The list of supported processors is constantly growing through continuous development of new JEDOS-IP. It is usable both in lab for design validation of prototypes as well as for production process and repair. The JEDOS technology is fully integrated into the software platform SYSTEM CASCON™. This enables the easy combination with Boundary Scan, Embedded Instruments and other non-invasive technologies on a single platform.
|JEDOS Application Manager||Core module of JEDOS, enables handling of functional IP’s, report generation and JTAG control|
|DDR Test||Functional at-speed / real time test of DDR devices with selectable algorithms (address test, burst test, noise test, stress test, cell test)|
|DDR Calibration||Functional Margin Test of DDR I/F with pre-defined parameters for the DDR RAM Controller, or automated search of case optimized parameters|
|Peripheral I/O Test||Functional at-speed / real time test of GPIO, UART, PCI, PCIe, Ethernet LAN, USB2.0, USB3.0|
|Universal Function Test||Load, execution and dynamic control of pre-compiled, JEDOS compliant IP generated by the user or from 3rd party for any kind of functional Test|
|In-System Device Programming||High speed programming of non-volatile devices like NAND, NOR, SPI, I2C, eMMC, MCU via streaming through communication I/F (USB2.0, USB3.0, LAN) or download from external connected USB Flash memory|