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Glossary

Glossary

/TRST

Test ReSeT

AAPG

Automatic Application Program Generator

ADYCS

Automatic DelaY CompenSation

AFPG

Automatic Flash Program Generator

AOI

Automated Optical Inspection

ATG

Automatic Test Generation

ATPG

Automatic Test Program Generator

Bareboard

"naked" Board

BScan

Boundary Scan (IEEE Std. 1149.x) is a technology for embedded access of IC pins by way of integrated scan cells. They form a shift register controlled via the Test Access Port (TAP). The principle was developed as an alternative to In-Circuit Test (ICT) to avoid the utilisation of nail probe contact.

Boundary Scan is part of the so called Embedded System Access (ESA) technologies, containing procedures such as Chip Embedded Instruments, Processor Emulation Test, In-System Programming or Core Assisted Programming. ESA technologies are currently the most modern strategies for validation, test and debug as well as programming of complex boards and systems. They can be applied throughout the entire product life cycle, enabling enhanced test coverage at reduced costs.

BSDL

Boundary Scan Description Language

BSDM

Boundary Scan Description Model

BST

Boundary Scan Test

CAD

Computer Aided Design

CASCON

Computer Aided SCan-based Observation and Node-control

CASLAN

CAScon LANguage

CDL

CASCON Device Library

CEM

Contract Electronic Manufactor

Chip embedded Instruments

Chip embedded Instruments are permanently integrated or temporarily implemented test and measurement functions (T&M) in an integrated circuit. Virtually, they are the counterpart to external T&M instruments as they don’t require invasive contacting by means of probes or nails. Hence, the problem of signal distortion in high-speed designs by parasitic contacting effects is omitted. Chip embedded Instruments are part of the so called Embedded System Access (ESA) technologies, featuring methods such as Boundary Scan, Processor Emulation Test, in-system programming or Core assisted Programming.

ChipVORX

ChipVORX is an IP-based technology for implementation, access and control of Chip embedded Instruments via IEEE Std. 1149.x/JTAG. It also supports FPGA embedded instruments in the form of softcores. The ChipVORX library currently contains more than 300 different test and measurement instruments for all leading FPGA platforms. Some of these instruments are frequency meters, high-speed Flash programmer as well as IP for at-speed access test of dynamic RAM devices. The usage of ChipVORX® requires neither expert background knowledge nor specific FPGA tools or continuous IP adjustments.

CNL

CASCON Net LIst

CON

CONfiguration file

EMS

Electronic Manufactoring Service

ESA technologies

ESA technologies are currently the most modern strategy for validation, test and debug as well as programming of complex boards and systems. They can be utilised throughout the entire product life cycle, enabling improved test coverage at reduced costs.

GENESIS

GOEPEL electronic Extended Support and Information Service

ICT

In Circuit Test

JBC

Jam Byte Code; Jam in binary format

PCB

Printed Circuit Board

POLARIS

Programming Of PLD and FLASH Reconfigurable In-System

PTH

Pin Through Hole

PTS

Program Type Selector

RAM

Random Access Memory

ScanVision tool suite

Basically, ScanVision consists of the three elements Layout Visualizer, Schematic Visualizer and Virtual Schematic Visualizer. All components are integral parts of the Boundary Scan system software SYSTEM CASCON, using a consistent project data base. This data base is generated by importing individual design data and interconnection referencing. For this purpose, appropriate tools are the CASCON Board Merger™ and CASCON Component Explorer.

Using this information provides opportunities for interactive cross-probing between schematic and layout, selective labelling of pins, components and circuits, as well as tracking of signal paths via multiple boards with dynamic switching. That enables operations such as test coverage analysis, hardware debugging or graphical fault display far above the board boundaries up to system level.

The enhanced ScanVision tools are integrated as standard starting from SYSTEM CASCON™ version 4.6.1 and are activated by the licence manager like the system software. For customers with a valid maintenance contract the new features are free of charge. SYSTEM CASCON™ is a professional JTAG/Boundary Scan development environment, developed by GOEPEL electronic currently with 45 completely integrated ISP, test, and debug tools for the support of all Embedded System Access technologies.

SCP

SCANPLUS

SMD

Service Mounted Device

SMT

Service Mounted Technology

STAPL

STandard Test And Programming Language

SVF

Serial Vector Format

TAP

Test Access Port

TCK

Test ClocK

TDI

Test Data In

TDO

Test Data Out

THT

Through Hole Technology

TMS

Test Mode Select

 

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Phone +44-1223-858298, Fax +44-1223-257800, www.goepel.co.uk